|
| enum class | CtrlPin : uint8_t { ENABLE = 0
, FAULT
, CMD
} |
| | Identifies the hardware control pins of the MAX22200. More...
|
| |
| enum class | GpioSignal : uint8_t { INACTIVE = 0
, ACTIVE = 1
} |
| | Abstract signal level for control pins. More...
|
| |
| enum class | DriveMode : uint8_t { CDR = 0
, VDR = 1
} |
| | Drive mode enumeration (VDRnCDR bit in CFG_CHx[7]) More...
|
| |
| enum class | SideMode : uint8_t { LOW_SIDE = 0
, HIGH_SIDE = 1
} |
| | High-side / Low-side selection (HSnLS bit in CFG_CHx[6]) More...
|
| |
| enum class | ChannelMode : uint8_t { INDEPENDENT = 0
, PARALLEL = 1
, HBRIDGE = 2
} |
| | Channel-pair mode (CMxy bits in STATUS[15:8]) More...
|
| |
| enum class | ChopFreq : uint8_t { FMAIN_DIV4 = 0
, FMAIN_DIV3 = 1
, FMAIN_DIV2 = 2
, FMAIN = 3
} |
| | Chopping frequency setting (FREQ_CFG bits in CFG_CHx[5:4]) More...
|
| |
| enum class | FaultType : uint8_t {
OCP = 0
, HHF = 1
, OLF = 2
, DPM = 3
,
OVT = 4
, UVM = 5
, COMER = 6
} |
| | Fault type enumeration. More...
|
| |
| enum class | FullBridgeState : uint8_t { HiZ = 0
, Forward = 1
, Reverse = 2
, Brake = 3
} |
| | Full-bridge state for a channel pair (datasheet Table 7) More...
|
| |
| enum class | DriverStatus : uint8_t {
OK = 0
, INITIALIZATION_ERROR
, COMMUNICATION_ERROR
, INVALID_PARAMETER
,
HARDWARE_FAULT
, TIMEOUT
} |
| | Driver operation result codes. More...
|
| |
| enum class | ChannelState : uint8_t {
DISABLED = 0
, ENABLED
, HIT_PHASE
, HOLD_PHASE
,
FAULT
} |
| | Logical channel state for application callbacks. More...
|
| |
|
| const char * | GetDriverVersion () noexcept |
| | Get the compiled driver version string (namespace-level convenience)
|
| |
| constexpr uint8_t | getChannelCfgBank (uint8_t channel) |
| | Get channel configuration register bank address.
|
| |
| uint32_t | getChopFreqKhz (bool master_clock_80khz, ChopFreq cf) |
| | Get chopping frequency in kHz for conversion (FREQM + FREQ_CFG)
|
| |
| float | getChopFreqKhzExact (bool master_clock_80khz, ChopFreq cf) |
| | Exact chopping frequency in kHz (FREQM + FREQ_CFG, datasheet Table 1)
|
| |
| uint8_t | currentMaToRaw (uint32_t full_scale_current_ma, uint32_t ma) |
| | Convert current in mA to 7-bit raw value (0–127) for CDR.
|
| |
| uint8_t | dutyPercentToRaw (float percent) |
| | Convert a VDR duty cycle in percent to the 7-bit HIT/HOLD field.
|
| |
| float | dutyRawToPercent (uint8_t raw) |
| | Convert the 7-bit VDR HIT/HOLD field to a duty cycle in percent (datasheet Table 3)
|
| |
| uint8_t | hitTimeMsToRaw (float ms, bool master_clock_80khz, ChopFreq cf) |
| | Convert HIT time in ms to 8-bit raw value (0–255)
|
| |
| float | getMaxHitTimeMs (bool master_clock_80khz, ChopFreq cf) |
| | Maximum representable HIT time in ms for raw values 1–254 (255 = continuous).
|
| |
| const char * | FaultTypeToStr (FaultType ft) |
| | Human-readable fault type name (for logging and tests)
|
| |
| const char * | DriverStatusToStr (DriverStatus s) |
| | Return a human-readable string for DriverStatus (for logging and tests)
|
| |
Channel-pair mode (CMxy bits in STATUS[15:8])
Configures pairs of contiguous channels (0-1, 2-3, 4-5, 6-7) for different operating modes. These bits can only be written when both channels in the pair are OFF (ONCHx = 0, ONCHy = 0).
INDEPENDENT (CMxy = 00)
- Each channel operates independently
- Standard half-bridge operation
- Each channel uses its own configuration register (CFG_CHx)
PARALLEL (CMxy = 01)
- Two channels connected in parallel to double current capability
- Output pins must be connected together externally
- Configuration taken from lower channel number (e.g., CFG_CH0 for pair 0-1)
- Higher channel's configuration register is ignored
- Activation remains independent (ONCHx and ONCHy control individually)
- TRGnSPI bits determine trigger source (see datasheet Table 6)
HBRIDGE (CMxy = 10)
- Two channels form a full-bridge (H-bridge) for bidirectional drive
- Used for latched (bi-stable) solenoid valves or brushed DC motors
- Four states: Hi-Z, Forward, Reverse, Brake (see datasheet Table 7)
- Forward mode uses CFG_CHy settings, Reverse mode uses CFG_CHx settings
- HSnLS bit is ignored in full-bridge mode
- TRGnSPI bits determine trigger source (see datasheet Table 8)
- Note
- Channel pairs: CM10 (ch0-1), CM32 (ch2-3), CM54 (ch4-5), CM76 (ch6-7)
-
CMxy = 11 is reserved — do not use
| Enumerator |
|---|
| INDEPENDENT | Channels independently controlled (CMxy = 00)
|
| PARALLEL | Channels in parallel mode (CMxy = 01) — double current.
|
| HBRIDGE | Channels in H-bridge mode (CMxy = 10) — bidirectional drive.
|
Chopping frequency setting (FREQ_CFG bits in CFG_CHx[5:4])
Selects the chopping frequency divider relative to the master frequency (FREQM). The actual chopping frequency fCHOP depends on both FREQM (STATUS[16]) and FREQ_CFG:
| FREQM | FREQ_CFG | fCHOP (kHz) | Period (μs) |
| 0 | 00 | 25 | 40 |
| 0 | 01 | 33.33 | 30 |
| 0 | 10 | 50 | 20 |
| 0 | 11 | 100 | 10 |
| 1 | 00 | 20 | 50 |
| 1 | 01 | 26.66 | 37.5 |
| 1 | 10 | 40 | 25 |
| 1 | 11 | 80 | 12.5 |
Effects of Chopping Frequency
- Higher frequency: Lower current ripple, better average current control, but higher switching losses and EMI
- Lower frequency: Higher current ripple, but lower switching losses
Duty Cycle Limits
Minimum and maximum duty cycles (δMIN, δMAX) depend on FREQM, FREQ_CFG, and SRC:
- SRC = 0 (Fast Mode):
- FREQ_CFG = 11: δMIN = 8%, δMAX = 92%
- Other FREQ_CFG: δMIN = 4%, δMAX = 96%
- SRC = 1 (Slew-Rate Controlled):
- FREQ_CFG = 01 or 00: δMIN = 7%, δMAX = 93%
- FREQ_CFG = 10 (FREQM=1 only): δMIN = 7%, δMAX = 93%
SRC + fCHOP restriction (datasheet)
SRC mode is only available for switching frequencies less than 50 kHz. When SRC = 1, use only FREQ_CFG that yields fCHOP < 50 kHz:
- FREQM = 0: use FMAIN_DIV4 (25 kHz) or FMAIN_DIV3 (33.33 kHz); do not use FMAIN_DIV2 (50 kHz) or FMAIN (100 kHz).
- FREQM = 1: use FMAIN_DIV4 (20 kHz), FMAIN_DIV3 (26.66 kHz), or FMAIN_DIV2 (40 kHz); do not use FMAIN (80 kHz).
- Note
- FREQ_CFG can be changed "on-the-fly" while channel is operating.
-
FREQM is a global setting in STATUS register (affects all channels).
| Enumerator |
|---|
| FMAIN_DIV4 | FreqMain / 4 (fCHOP = 25kHz if FREQM=0, 20kHz if FREQM=1). Valid with SRC=1.
|
| FMAIN_DIV3 | FreqMain / 3 (fCHOP = 33.33kHz if FREQM=0, 26.66kHz if FREQM=1). Valid with SRC=1.
|
| FMAIN_DIV2 | FreqMain / 2 (fCHOP = 50kHz if FREQM=0, 40kHz if FREQM=1). With SRC=1 use only if FREQM=1 (40kHz).
|
| FMAIN | FreqMain (fCHOP = 100kHz if FREQM=0, 80kHz if FREQM=1). Not valid with SRC=1.
|
Full-bridge state for a channel pair (datasheet Table 7)
For a pair (x, y) = (0,1), (2,3), (4,5), or (6,7): ONCHy and ONCHx determine the bridge state. Forward uses CFG_CHy; Reverse uses CFG_CHx.
| Enumerator |
|---|
| HiZ | ONCHx=0, ONCHy=0 — high impedance (both switches off)
|
| Forward | ONCHx=1, ONCHy=0 — forward (control from CFG_CHy)
|
| Reverse | ONCHx=0, ONCHy=1 — reverse (control from CFG_CHx)
|
| Brake | ONCHx=1, ONCHy=1 — brake (both outputs driven to GND)
|
| uint8_t max22200::dutyPercentToRaw |
( |
float |
percent | ) |
|
|
inline |
Convert a VDR duty cycle in percent to the 7-bit HIT/HOLD field.
In VDR the HIT[6:0] and HOLD[6:0] fields hold the duty cycle in percent (datasheet Table 3, "VDR Duty Cycle"): 0 is 0 %, values from δMIN to δMAX are that duty in 1 % steps, 100 and above is 100 %. The chip clamps 1..δMIN and δMAX..99 to δMIN / δMAX itself.
- Parameters
-
| percent | Duty cycle in percent |
- Returns
- Raw 7-bit value: round(percent), 0 for percent <= 0, 100 for percent >= 100
