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| constexpr uint8_t | STATUS = 0x00 |
| | Status register (32-bit) — channel on/off, HW config, faults, ACTIVE.
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| constexpr uint8_t | CFG_CH0 = 0x01 |
| | Channel 0 configuration register (32-bit)
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| constexpr uint8_t | CFG_CH1 = 0x02 |
| | Channel 1 configuration register (32-bit)
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| constexpr uint8_t | CFG_CH2 = 0x03 |
| | Channel 2 configuration register (32-bit)
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| constexpr uint8_t | CFG_CH3 = 0x04 |
| | Channel 3 configuration register (32-bit)
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| constexpr uint8_t | CFG_CH4 = 0x05 |
| | Channel 4 configuration register (32-bit)
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| constexpr uint8_t | CFG_CH5 = 0x06 |
| | Channel 5 configuration register (32-bit)
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| constexpr uint8_t | CFG_CH6 = 0x07 |
| | Channel 6 configuration register (32-bit)
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| constexpr uint8_t | CFG_CH7 = 0x08 |
| | Channel 7 configuration register (32-bit)
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| constexpr uint8_t | FAULT = 0x09 |
| | Fault register (32-bit, read-only) — per-channel fault flags.
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| constexpr uint8_t | CFG_DPM = 0x0A |
| | DPM configuration register (32-bit) — global DPM algorithm settings.
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| |
Register bank addresses for MAX22200.
These addresses are used in the Command Register's A_BNK field (bits 4:1) to select which 32-bit register to access. Each register is addressed by a 4-bit bank address (0x00-0x0A).
- Note
- The Command Register itself is not addressed via A_BNK — it is written directly when CMD pin is HIGH.