|
| constexpr uint32_t | ONCH_SHIFT = 24 |
| | ONCH bit shift (bits 31:24)
|
| |
| constexpr uint32_t | ONCH_MASK = 0xFF000000u |
| | ONCH bitmask.
|
| |
| constexpr uint32_t | M_OVT_BIT = (1u << 23) |
| | OVT fault mask (1=masked, 0=signaled)
|
| |
| constexpr uint32_t | M_OCP_BIT = (1u << 22) |
| | OCP fault mask.
|
| |
| constexpr uint32_t | M_OLF_BIT = (1u << 21) |
| | OLF fault mask.
|
| |
| constexpr uint32_t | M_HHF_BIT = (1u << 20) |
| | HHF fault mask.
|
| |
| constexpr uint32_t | M_DPM_BIT = (1u << 19) |
| | DPM fault mask.
|
| |
| constexpr uint32_t | M_COMF_BIT = (1u << 18) |
| | Communication fault mask (reset value = 1, masked by default)
|
| |
| constexpr uint32_t | M_UVM_BIT = (1u << 17) |
| | UVM fault mask.
|
| |
| constexpr uint32_t | FREQM_BIT = (1u << 16) |
| | Master frequency (0=100kHz, 1=80kHz)
|
| |
| constexpr uint32_t | CM76_SHIFT = 14 |
| | CM76 bit shift (bits 15:14)
|
| |
| constexpr uint32_t | CM76_MASK = (0x03u << 14) |
| | CM76 bitmask.
|
| |
| constexpr uint32_t | CM54_SHIFT = 12 |
| | CM54 bit shift (bits 13:12)
|
| |
| constexpr uint32_t | CM54_MASK = (0x03u << 12) |
| | CM54 bitmask.
|
| |
| constexpr uint32_t | CM32_SHIFT = 10 |
| | CM32 bit shift (bits 11:10)
|
| |
| constexpr uint32_t | CM32_MASK = (0x03u << 10) |
| | CM32 bitmask.
|
| |
| constexpr uint32_t | CM10_SHIFT = 8 |
| | CM10 bit shift (bits 9:8)
|
| |
| constexpr uint32_t | CM10_MASK = (0x03u << 8) |
| | CM10 bitmask.
|
| |
| constexpr uint32_t | OVT_BIT = (1u << 7) |
| | Overtemperature fault flag (read-only)
|
| |
| constexpr uint32_t | OCP_BIT = (1u << 6) |
| | Overcurrent fault flag (read-only)
|
| |
| constexpr uint32_t | OLF_BIT = (1u << 5) |
| | Open-load fault flag (read-only)
|
| |
| constexpr uint32_t | HHF_BIT = (1u << 4) |
| | HIT current not reached flag (read-only)
|
| |
| constexpr uint32_t | DPM_BIT = (1u << 3) |
| | Plunger movement detection flag (read-only)
|
| |
| constexpr uint32_t | COMER_BIT = (1u << 2) |
| |
| constexpr uint8_t | FAULT_BYTE_COMER = 0x04u |
| | Fault byte value returned on SDO when COMER is set (per datasheet Figure 6)
|
| |
| constexpr uint32_t | UVM_BIT = (1u << 1) |
| | Undervoltage flag (read-only, set at POR, cleared by read)
|
| |
| constexpr uint32_t | ACTIVE_BIT = (1u << 0) |
| | Global enable bit (write: 0=low-power, 1=normal operation)
|
| |
| constexpr uint32_t | FAULT_FLAGS_MASK = 0xFEu |
| | Fault flags byte mask (bits 7:1, read-only)
|
| |
| constexpr uint8_t | CM_INDEPENDENT = 0x00 |
| | Channel-pair mode: independent operation.
|
| |
| constexpr uint8_t | CM_PARALLEL = 0x01 |
| | Channel-pair mode: parallel mode (double current)
|
| |
| constexpr uint8_t | CM_HBRIDGE = 0x02 |
| | Channel-pair mode: H-bridge mode (full-bridge)
|
| |
| constexpr uint8_t | CM_RESERVED = 0x03 |
| | Channel-pair mode: reserved (do not use)
|
| |
STATUS register bit field definitions.
The STATUS register is 32-bit and contains channel activation, hardware configuration, fault masks, fault flags, and the global ACTIVE bit.
Register Layout
| Byte | Bits | Field | Description |
| 3 | 31:24 | ONCH[7:0] | Channel on/off bits (1=on, 0=off) |
| 2 | 23:16 | M_OVT, M_OCP, etc. | Fault mask bits + FREQM |
| 1 | 15:8 | CM76, CM54, etc. | Channel-pair mode configuration |
| 0 | 7:0 | OVT, OCP, etc. | Fault flags (read-only) + ACTIVE |
Key Fields
- ONCH[7:0]: Individual channel enable/disable. Bit N controls channel N. Can be updated with fast 8-bit write to STATUS[31:24].
- ACTIVE: Global enable bit. Must be set to 1 for normal operation. When 0, device enters low-power mode and all channels are three-stated. Default is 0 at power-up.
- UVM: Undervoltage flag. Set high at power-up and must be cleared by reading the STATUS register. Reading STATUS clears UVM and deasserts nFAULT.
- CMxy: Channel-pair mode bits (CM76, CM54, CM32, CM10). Configure pairs of contiguous channels for independent, parallel, or H-bridge operation. Can only be written when both channels in the pair are OFF (ONCHx=0, ONCHy=0).
- Note
- Fault flags (bits 7:1) are read-only. They are cleared by reading the STATUS register (UVM) or FAULT register (OCP, HHF, OLF, DPM).
