max22200::CommandReg Namespace Reference

Command Register bit field definitions and helper functions. More...

Functions
constexpr uint8_t	build (uint8_t bank, bool write, bool mode8=false)
	Build a Command Register value.

Variables
constexpr uint8_t	RBW_POS = 7
	Read/Write bit position.
constexpr uint8_t	RBW_READ = 0x00
	Read operation (bit 7 = 0)
constexpr uint8_t	RBW_WRITE = 0x80
	Write operation (bit 7 = 1)
constexpr uint8_t	A_BNK_POS = 1
	Bank address bit position (bits 4:1)
constexpr uint8_t	A_BNK_MASK = 0x1E
	Bank address mask (bits 4:1)
constexpr uint8_t	MODE_8BIT = 0x01
	8-bit MSB only access (bit 0 = 1)
constexpr uint8_t	MODE_32BIT = 0x00
	32-bit full access (bit 0 = 0)

Detailed Description

Command Register bit field definitions and helper functions.

The Command Register is 8-bit, write-only, and must be written with CMD pin HIGH before any register access. It determines the type and format of the follow-on SPI transfer.

Bit Layout

Bit:  7     6     5     4     3     2     1     0
     RB/W  RFU   RFU   A_BNK[3] A_BNK[2] A_BNK[1] A_BNK[0]  8bit/n32

Protocol Sequence

1. Set CMD pin HIGH
2. Write Command Register (1 byte transfer)
   • Device responds with STATUS[7:0] on SDO (Fault Flag Byte)
   • Check for communication error: STATUS[7:0] = 0x04 (COMER flag)
3. Set CMD pin LOW
4. Perform data transfer (1 byte for 8-bit mode, 4 bytes for 32-bit mode)

Note

Once the Command Register is written, all subsequent SPI transfers remain of the same type (8-bit or 32-bit) until the Command Register is rewritten.

The CMD pin must be held HIGH during the rising edge of CSB (chip select).

Function Documentation

build()

constexpr uint8_t max22200::CommandReg::build ( uint8_t  bank, bool  write, bool  mode8 = false  )

constexpr

Build a Command Register value.

Constructs the 8-bit Command Register byte from the register bank address, read/write mode, and transfer size.

Parameters

bank	Register bank address (0x00-0x0A, see RegBank namespace)
write	true for write operation, false for read
mode8	true for 8-bit MSB only, false for 32-bit full register

Returns

8-bit command register value ready for SPI transfer

Example

// Write 32-bit STATUS register
uint8_t cmd = CommandReg::build(RegBank::STATUS, true, false);
// Result: 0x80 | (0x00 << 1) | 0x00 = 0x80
 
// Read 8-bit MSB of CFG_CH0 (fast HOLD current update)
uint8_t cmd = CommandReg::build(RegBank::CFG_CH0, false, true);
// Result: 0x00 | (0x01 << 1) | 0x01 = 0x03

Variable Documentation

A_BNK_MASK

constexpr uint8_t max22200::CommandReg::A_BNK_MASK = 0x1E

constexpr

Bank address mask (bits 4:1)

A_BNK_POS

constexpr uint8_t max22200::CommandReg::A_BNK_POS = 1

constexpr

Bank address bit position (bits 4:1)

MODE_32BIT

constexpr uint8_t max22200::CommandReg::MODE_32BIT = 0x00

constexpr

32-bit full access (bit 0 = 0)

MODE_8BIT

constexpr uint8_t max22200::CommandReg::MODE_8BIT = 0x01

constexpr

8-bit MSB only access (bit 0 = 1)

RBW_POS

constexpr uint8_t max22200::CommandReg::RBW_POS = 7

constexpr

Read/Write bit position.

RBW_READ

constexpr uint8_t max22200::CommandReg::RBW_READ = 0x00

constexpr

Read operation (bit 7 = 0)

RBW_WRITE

constexpr uint8_t max22200::CommandReg::RBW_WRITE = 0x80

constexpr

Write operation (bit 7 = 1)