|
| constexpr uint32_t | HFS_BIT = (1u << 31) |
| | HFS bit (0=1x full-scale, 1=0.5x half-scale)
|
| |
| constexpr uint32_t | HOLD_SHIFT = 24 |
| | HOLD current bit shift.
|
| |
| constexpr uint32_t | HOLD_MASK = (0x7Fu << 24) |
| | HOLD current mask (7-bit, 0-127)
|
| |
| constexpr uint32_t | TRGNSPI_BIT = (1u << 23) |
| | TRGnSPI bit (0=SPI ONCH, 1=TRIG pin)
|
| |
| constexpr uint32_t | HIT_SHIFT = 16 |
| | HIT current bit shift.
|
| |
| constexpr uint32_t | HIT_MASK = (0x7Fu << 16) |
| | HIT current mask (7-bit, 0-127)
|
| |
| constexpr uint32_t | HITT_SHIFT = 8 |
| | HIT time bit shift.
|
| |
| constexpr uint32_t | HITT_MASK = (0xFFu << 8) |
| | HIT time mask (8-bit, 0-255)
|
| |
| constexpr uint32_t | VDRNCDR_BIT = (1u << 7) |
| | VDRnCDR bit (0=CDR, 1=VDR)
|
| |
| constexpr uint32_t | HSNLS_BIT = (1u << 6) |
| | HSnLS bit (0=low-side, 1=high-side)
|
| |
| constexpr uint32_t | FREQ_CFG_SHIFT = 4 |
| | FREQ_CFG bit shift.
|
| |
| constexpr uint32_t | FREQ_CFG_MASK = (0x03u << 4) |
| | FREQ_CFG mask (2-bit)
|
| |
| constexpr uint32_t | SRC_BIT = (1u << 3) |
| | SRC bit (0=fast, 1=slew-rate controlled)
|
| |
| constexpr uint32_t | OL_EN_BIT = (1u << 2) |
| | OL_EN bit (0=disabled, 1=enabled)
|
| |
| constexpr uint32_t | DPM_EN_BIT = (1u << 1) |
| | DPM_EN bit (0=disabled, 1=enabled)
|
| |
| constexpr uint32_t | HHF_EN_BIT = (1u << 0) |
| | HHF_EN bit (0=disabled, 1=enabled)
|
| |
| constexpr uint8_t | MAX_HOLD = 127 |
| | Maximum HOLD current register value (7-bit)
|
| |
| constexpr uint8_t | MAX_HIT = 127 |
| | Maximum HIT current register value (7-bit)
|
| |
| constexpr uint8_t | MAX_HIT_TIME = 255 |
| | Maximum HIT time register value (8-bit)
|
| |
| constexpr uint8_t | CONTINUOUS_HIT = 255 |
| | HIT time value for continuous IHIT (tHIT = ∞)
|
| |
Channel configuration register bit field definitions.
Each channel has one 32-bit configuration register (CFG_CHx) that contains all drive parameters for that channel. The register layout is:
Register Layout
| Byte | Bits | Field | Description |
| 3 | 31 | HFS | Half Full-Scale (0=1x, 1=0.5x) |
| 3 | 30:24 | HOLD[6:0] | HOLD current (7-bit, 0-127) |
| 2 | 23 | TRGnSPI | Trigger source (0=SPI, 1=TRIG pin) |
| 2 | 22:16 | HIT[6:0] | HIT current (7-bit, 0-127) |
| 1 | 15:8 | HIT_T[7:0] | HIT time (8-bit, 0-255) |
| 0 | 7 | VDRnCDR | Drive mode (0=CDR, 1=VDR) |
| 0 | 6 | HSnLS | High-side/Low-side (0=LS, 1=HS) |
| 0 | 5:4 | FREQ_CFG | Chopping frequency divider |
| 0 | 3 | SRC | Slew rate control enable |
| 0 | 2 | OL_EN | Open load detect enable |
| 0 | 1 | DPM_EN | DPM detection enable |
| 0 | 0 | HHF_EN | HIT current check enable |
Current Programming (CDR Mode)
In CDR mode, HIT and HOLD currents are programmed as fractions of the full-scale current (IFS):
- IHIT = HIT[6:0] / 127 × IFS (for 1-126)
- IHOLD = HOLD[6:0] / 127 × IFS (for 1-126)
- HIT[6:0] = 0: HS switch ON, LS switch OFF
- HIT[6:0] = 127: HS switch OFF, LS switch ON
The full-scale current IFS is set by an external resistor RREF on the IREF pin:
- IFS = KFS × 1V / RREF
- KFS = 15k when HFS = 0 (full-scale, IFS up to 1A)
- KFS = 7.5k when HFS = 1 (half-scale, IFS up to 0.5A)
- RREF range: 15kΩ to 100kΩ recommended
Current Programming (VDR Mode)
In VDR mode, HIT and HOLD values represent PWM duty cycle percentages:
- Duty cycle = HIT[6:0]% (for 1-126, clamped to δMIN-δMAX per Table 2)
- Duty cycle = 0% when HIT[6:0] = 0
- Duty cycle = 100% when HIT[6:0] ≥ 100
HIT Time Programming
The HIT excitation time is calculated as:
- HIT_T[7:0] = 0: No HIT time (tHIT = 0)
- HIT_T[7:0] = 1-254: tHIT = HIT_T[7:0] × 40 / fCHOP
- HIT_T[7:0] = 255: Continuous IHIT (tHIT = ∞)
Where fCHOP is the chopping frequency (depends on FREQM and FREQ_CFG).
Chopping Frequency
The chopping frequency fCHOP depends on FREQM (STATUS[16]) and FREQ_CFG[1:0]:
| FREQM | FREQ_CFG | fCHOP (kHz) |
| 0 | 00 | 25 |
| 0 | 01 | 33.33 |
| 0 | 10 | 50 |
| 0 | 11 | 100 |
| 1 | 00 | 20 |
| 1 | 01 | 26.66 |
| 1 | 10 | 40 |
| 1 | 11 | 80 |
Restrictions
- VDRnCDR and HSnLS bits can only be modified when:
- All channels are OFF (ONCHx = 0 for all channels)
- Both TRIGA and TRIGB inputs are logic-low
- CDR mode is only supported in low-side operation (HSnLS = 0)
- High-side mode (HSnLS = 1) only supports VDR mode
- HFS bit is only available for low-side applications
- Note
- Per MAX22200 datasheet Table 11 and sections on Current Drive Regulation and Voltage Drive Regulation.
