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HardFOC driver

MAX22200 Driver

A C++20 driver for the Analog Devices MAX22200 octal solenoid and motor driver. It brings the chip up, configures each half-bridge for current or voltage drive with HIT and HOLD levels, switches channels, runs bridges and reads faults, on any MCU with SPI.

Quickstart API guide Source on GitHub

The driver has no platform code. You give it a small class that moves bytes over SPI and drives the ENABLE and CMD pins; it does the rest: the two-phase command and data protocol, the power-up sequence, register encoding in milliamps, percent and milliseconds, and fault decoding.

Octal serial-controlled solenoid and motor driver MAX22200 Analog Devices (Maxim Integrated)
Outputs
8 push-pull half-bridges, 0.2 Ω typical, up to 1 A RMS each; pairs in parallel or as full bridges
Drive
Current regulation (CDR, integrated current sensing, low side) or voltage regulation (VDR, PWM duty)
HIT and HOLD
7-bit HIT and HOLD level and 8-bit HIT time per channel; chopping at 20 kHz to 100 kHz
Host interface
SPI mode 0 up to 10 MHz (5 MHz daisy-chained); the CMD pin selects command or data
Control pins
ENABLE, CMD, TRIGA, TRIGB (inputs); FAULT (open-drain output)
Supply
VM 4.5 V to 36 V; logic inputs switch at 1.2 V and take up to 6 V
Package
32-pin TQFN 5 mm × 5 mm, −40 °C to +85 °C; the MAX22200A adds selective fault clear

Datasheet (Rev. 1, 3/25) · Product page

What you get

  • One object per chip. MAX22200<YourSpi> takes your port and the board's full-scale current, and runs the datasheet's start-up flow in Initialize(). See API guide.
  • Real units. HIT and HOLD in milliamps (CDR) or percent (VDR), HIT time in milliseconds, converted with the board's RREF and the chip's chopping frequency. See Drive modes.
  • Fast switching. Turning channels on and off is one 8-bit write of the ONCH byte; full-bridge pairs take forward, reverse, brake and Hi-Z. See API guide.
  • Faults by channel. STATUS flags, per-channel OCP, HHF, open-load and plunger-movement flags, selective clear on the MAX22200A and the FAULT pin. See API guide.
  • Zero-overhead portability. The port is a CRTP class: no virtual calls, no heap, no RTOS dependency. See Porting.
  • Tested without hardware. Host unit tests run the driver against a model of the chip's SPI protocol. See Testing and CI.

Where to go next

  • Quickstart

    Wire the chip, write the port, pull in a solenoid in about 15 lines.

  • Hardware

    Pins, bus settings, timing, supply and the full-scale current resistor.

  • Architecture

    The three layers and what each one owns.

  • API guide

    Configure, switch, read and handle faults, task by task.

  • Porting

    Implement the SPI interface for your MCU.

  • API reference

    Every class and member, generated from the headers.