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HardFOC driver

PF1550 Driver

A header-only C++20 driver for the NXP PF1550 power management IC. It identifies the chip, applies board power profiles, sets rail voltages and the USB input limit, reads OTP, and reports rail state and faults, on any MCU with I2C.

Quickstart API guide Source on GitHub

The driver has no platform code. You give it a small class that reads and writes one register over I2C and sets three strap pins; it does the rest: identification, ordered register sequences, code tables, the OTP unlock sequence and fault decoding.

PMIC for low-power application processors PF1550 NXP Semiconductors
Regulators
SW1, SW2, SW3 buck converters (1.0 A each); LDO1 and LDO3 (300 mA), LDO2 (400 mA); VSNVS 3.0 V; VREFDDR
Charger
Single-cell Li-ion / Li-polymer linear charger; VBUSIN 4.1 V to 6.0 V, input limit 10 mA to 1500 mA
Host interface
I2C, fast mode up to 400 kHz, 7-bit address 0x08 (OTP-selectable 0x08 to 0x0F)
Control pins
STANDBY, PWRON, ONKEY, WDI (inputs); INTB, RESETBMCU (open-drain outputs)
Configuration
OTP: start-up sequence, set points, charger parameters; A0EP parts ship unprogrammed
Package
40-pin HVQFN, 5 mm × 5 mm, exposed pad; −40 °C to 105 °C (MC34) or 85 °C (MC32)

Data sheet (Rev. 7) · Product page · Register map

What you get

  • One object per PMIC. PF1550<YourBus> exposes identification, register access, profiles, rail set points, strap pins, OTP, interrupts and diagnostics as plain member functions. See API guide.
  • Board profiles as data. A profile is a table of register writes with optional waits, applied in order; the Portenta H7 default and carrier profiles are included. See Portenta H7 profiles.
  • Datasheet code tables. SW, LDO and VBUS-limit codes convert to millivolts and milliamps from the data sheet's tables, checked at compile time. See Rails and OTP.
  • A diagnostic snapshot. One call reads identity, state, every rail's set point and enables, the VBUS limit and latched faults, for a monitor task. See API guide.
  • Zero-overhead portability. The port is a CRTP class: no virtual calls, no heap, no RTOS dependency. See Porting.
  • Tested without hardware. Host unit tests run the driver against a register model of the chip. See Testing and CI.

Where to go next

  • Quickstart

    Wire the bus, write the port, read the rails in about 15 lines.

  • Hardware

    Pins, bus settings, supplies, rails and the parts.

  • Architecture

    The three layers and what each one owns.

  • API guide

    Identify, configure, read, diagnose and handle faults, task by task.

  • Porting

    Implement the bus interface for your MCU.

  • API reference

    Every class and member, generated from the headers.