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| | StmSpiDevice (StmSpiBus *parent, const hf_spi_device_config_t &config) noexcept |
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| | ~StmSpiDevice () noexcept override |
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| bool | Initialize () noexcept override |
| | Initialize the SPI bus.
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| bool | Deinitialize () noexcept override |
| | Deinitialize the SPI bus.
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| hf_spi_err_t | Transfer (const hf_u8_t *tx_data, hf_u8_t *rx_data, hf_u16_t length, hf_u32_t timeout_ms=0) noexcept override |
| | One soft-CS frame: bus lock + mode + FIFO flush + CS RAII + HAL.
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| hf_spi_err_t | TransferChain (const hf_u8_t *const *tx_frames, hf_u8_t *const *rx_frames, hf_u16_t frame_length, hf_u16_t frame_count, hf_u32_t inter_frame_gap_us, hf_u32_t timeout_ms=0) noexcept override |
| | N soft-CS frames under one bus lock (CS still toggles per frame).
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| const void * | GetDeviceConfig () const noexcept override |
| | Get the device configuration for this SPI device.
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| void | IdleChipSelect () noexcept override |
| | Force soft-CS idle-high (shared-bus peer park before Mode1 identity).
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| void | HoldChipSelectMs (hf_u32_t ms) noexcept override |
| | Bus-locked soft-CS hold for pad proof (peers idle-high).
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| bool | SetTransferMode (hf_u8_t mode_0_to_3) noexcept override |
| | Set CPOL/CPHA for the next transfer (0=Mode0 … 3=Mode3).
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| bool | SetIoSwap (bool enable) noexcept override |
| | Set MOSI↔MISO IOSwap for the next transfer (CFG2 IOSWP).
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| const hf_spi_device_config_t & | GetConfig () const noexcept |
| | Device configuration (CS port/pin, mode, clock hint).
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| virtual | ~BaseSpi () noexcept=default |
| | Virtual destructor ensures proper cleanup in derived classes.
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| | BaseSpi (const BaseSpi &)=delete |
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| BaseSpi & | operator= (const BaseSpi &)=delete |
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| | BaseSpi (BaseSpi &&)=delete |
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| BaseSpi & | operator= (BaseSpi &&)=delete |
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| bool | EnsureInitialized () noexcept |
| | Ensures that the SPI bus is initialized (lazy initialization).
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| bool | EnsureDeinitialized () noexcept |
| | Ensures that the SPI bus is deinitialized (lazy deinitialization).
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| bool | IsInitialized () const noexcept |
| | Checks if the bus is initialized.
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| virtual bool | Open () noexcept |
| | Legacy compatibility: Open and initialize the SPI bus.
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| virtual bool | Close () noexcept |
| | Legacy compatibility: Close and de-initialize the SPI bus.
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| virtual bool | Transfer (const hf_u8_t *tx_data, hf_u8_t *rx_data, hf_u16_t length) noexcept |
| | Legacy compatibility: Transfer with boolean return.
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| virtual hf_spi_err_t | Write (const hf_u8_t *data, hf_u16_t length, hf_u32_t timeout_ms=0) noexcept |
| | Write data to SPI bus.
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| virtual hf_spi_err_t | Read (hf_u8_t *data, hf_u16_t length, hf_u32_t timeout_ms=0) noexcept |
| | Read data from SPI bus.
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| virtual bool | Write (const hf_u8_t *data, hf_u16_t length) noexcept |
| | Legacy compatibility: Write with boolean return.
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| virtual bool | Read (hf_u8_t *data, hf_u16_t length) noexcept |
| | Legacy compatibility: Read with boolean return.
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| virtual bool | WriteByte (hf_u8_t data) noexcept |
| | Write single byte to SPI bus.
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| virtual bool | ReadByte (hf_u8_t &data) noexcept |
| | Read single byte from SPI bus.
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| virtual bool | TransferByte (hf_u8_t tx_data, hf_u8_t &rx_data) noexcept |
| | Write single byte and read response.
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| virtual hf_spi_err_t | ResetStatistics () noexcept |
| | Reset SPI operation statistics.
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| virtual hf_spi_err_t | ResetDiagnostics () noexcept |
| | Reset SPI diagnostic information.
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| virtual hf_spi_err_t | GetStatistics (hf_spi_statistics_t &statistics) const noexcept |
| | Get SPI operation statistics.
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| virtual hf_spi_err_t | GetDiagnostics (hf_spi_diagnostics_t &diagnostics) const noexcept |
| | Get SPI diagnostic information.
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| |
Soft-CS SPI slave on a shared StmSpiBus.
Owns one GPIO chip-select and a per-device SPI mode (hf_spi_device_config_t::mode). Each Transfer:
- Takes StmSpiBusLock (RTOS mutex — peers wait),
- Parks all soft-CS on the bus idle-high,
- Applies this device's CPOL/CPHA (SPE toggle only with every CS high),
- Flushes the RX FIFO,
- Scopes only this CS with SoftChipSelectGuard,
- Releases the bus lock.
Mixed Mode 0/1/3 slaves may share one CubeMX SPI peripheral. Chip handlers and external drivers must not poke CS — only Transfer / TransferChain.
- Note
- CS low during a Mode1 (TLE) frame is expected. CS must be high for every other slave while Mode0/1/3 SPE/CPOL is being rewritten.