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Internal Interface Wrap
API reference
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SPI device configuration for STM32. More...
#include <EspTypes_SPI.h>
Public Member Functions | |
| hf_spi_device_config_t () noexcept | |
| hf_spi_device_config_t () noexcept | |
Public Attributes | |
| hf_u32_t | clock_speed_hz |
| Device clock speed (Hz) | |
| hf_spi_mode_t | mode |
| SPI mode (0-3) | |
| hf_pin_num_t | cs_pin |
| CS pin (or -1 for software CS) | |
| hf_u8_t | queue_size |
| Transaction queue size. | |
| hf_u8_t | command_bits |
| Command phase bits (0-16) | |
| hf_u8_t | address_bits |
| Address phase bits (0-64) | |
| hf_u8_t | dummy_bits |
| Dummy bits between address and data. | |
| hf_u16_t | duty_cycle_pos |
| Duty cycle of positive clock (1/256th, 128=50%) | |
| hf_u16_t | cs_ena_pretrans |
| CS active before transmission (bit-cycles) | |
| hf_u8_t | cs_ena_posttrans |
| CS active after transmission (bit-cycles) | |
| hf_u32_t | flags |
| Bitwise OR of SPI_DEVICE_* flags. | |
| hf_u32_t | input_delay_ns |
| Input delay (ns) | |
| void(* | pre_cb )(void *) |
| Pre-transfer callback (optional) | |
| void(* | post_cb )(void *) |
| Post-transfer callback (optional) | |
| void * | user_ctx |
| User context for callbacks. | |
| hf_spi_clock_source_t | clock_source |
| Clock source selection (0=default, ESP32 specific) | |
| hf_spi_sampling_point_t | sampling_point |
| Sampling point for data (ESP32 specific) | |
| hf_stm32_spi_mode_t | mode |
| CPOL/CPHA applied per-transfer by StmSpiBus. | |
| GPIO_TypeDef * | cs_port |
| CS GPIO port (e.g., GPIOA) | |
| hf_u16_t | cs_pin |
| CS GPIO pin mask (e.g., GPIO_PIN_4) | |
| bool | cs_active_low |
| CS active low (default: true) | |
| hf_u8_t | inter_data_idle_cycles |
| SCK idle cycles the master inserts between data frames (H7 SPI CFG2.MIDI, 0–15), applied per-transfer with CPOL/CPHA. | |
SPI device configuration for STM32.
Platform-agnostic SPI device configuration structure for ESP32.
This structure provides all configuration options for registering a device on an SPI bus, including clock, mode, CS, queue, DMA, callbacks, and advanced ESP-IDF v5.5+ features. All fields use project types for portability.
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inlinenoexcept |
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inlinenoexcept |
| hf_spi_device_config_t::address_bits |
Address phase bits (0-64)
Address phase bits (0-64)
| hf_spi_device_config_t::clock_source |
Clock source selection (0=default, ESP32 specific)
Clock source selection for ESP32 (0=default, see spi_clock_source_t)
| hf_u32_t hf_spi_device_config_t::clock_speed_hz |
Device clock speed (Hz)
Target SCK frequency (Hz), applied per-transfer via CFG1.MBR.
StmSpiBus::ApplyDeviceMode picks the smallest prescaler whose resulting SCK does not exceed this value, so the effective clock is always ≤ the request. Peers on one peripheral may therefore run at different speeds: a shift-register slave (TLE92466ED, 8 MHz) does not have to inherit the prescaler a firmware-serviced slave (TMC9660) needs.
Before this was honored the whole bus ran at the CubeMX prescaler, which had been slowed to /256 for the TMC9660 — the TLE paid a 68 µs wire time per 32-bit frame instead of 8 µs.
Device clock speed in Hz
| hf_spi_device_config_t::command_bits |
Command phase bits (0-16)
Command phase bits (0-16)
| bool hf_spi_device_config_t::cs_active_low |
CS active low (default: true)
| hf_spi_device_config_t::cs_ena_posttrans |
CS active after transmission (bit-cycles)
CS active after transmission (bit-cycles)
| hf_spi_device_config_t::cs_ena_pretrans |
CS active before transmission (bit-cycles)
CS active before transmission (bit-cycles)
| hf_spi_device_config_t::cs_pin |
CS pin (or -1 for software CS)
CS pin number (or -1 for software CS)
| GPIO_TypeDef* hf_spi_device_config_t::cs_port |
CS GPIO port (e.g., GPIOA)
| hf_spi_device_config_t::dummy_bits |
Dummy bits between address and data.
Dummy bits between address and data
| hf_spi_device_config_t::duty_cycle_pos |
Duty cycle of positive clock (1/256th, 128=50%)
Duty cycle of positive clock (1/256th, 128=50%)
| hf_spi_device_config_t::flags |
Bitwise OR of SPI_DEVICE_* flags.
Bitwise OR of SPI_DEVICE_* flags
| hf_spi_device_config_t::input_delay_ns |
Input delay (ns)
Input delay in nanoseconds
| hf_u8_t hf_spi_device_config_t::inter_data_idle_cycles |
SCK idle cycles the master inserts between data frames (H7 SPI CFG2.MIDI, 0–15), applied per-transfer with CPOL/CPHA.
With 8-bit DataSize a multi-byte word is clocked as several data frames, so a non-zero value pauses SCK mid-word at every byte boundary. Slaves with firmware-serviced FIFOs (TMC9660 parameter mode) need the pause to refill; slaves that shift a hardware register through one CS window (TLE92466ED 32-bit frames) expect a continuous bit stream and are configured with 0. Default 15 preserves the bus-wide behavior that predates this field.
| hf_spi_device_config_t::mode |
SPI mode (0-3)
SPI mode (0-3)
| hf_stm32_spi_mode_t hf_spi_device_config_t::mode |
CPOL/CPHA applied per-transfer by StmSpiBus.
| hf_spi_device_config_t::post_cb |
Post-transfer callback (optional)
Post-transfer callback (optional)
| hf_spi_device_config_t::pre_cb |
Pre-transfer callback (optional)
Pre-transfer callback (optional)
| hf_spi_device_config_t::queue_size |
Transaction queue size.
Transaction queue size
| hf_spi_sampling_point_t hf_spi_device_config_t::sampling_point |
Sampling point for data (ESP32 specific)
| hf_spi_device_config_t::user_ctx |
User context for callbacks.
User context for callbacks
1.9.8