flux_hal_valve.hpp File Reference

ValveBank facade, first slice: the hardware enable path of both valve banks. More...

#include "flux_hal/flux_hal_types.hpp"

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Classes
struct	flux::hal::ValveBank
	Both valve banks, as one hardware-gated actuator group. More...

Namespaces
namespace	flux
namespace	flux::hal

Detailed Description

ValveBank facade, first slice: the hardware enable path of both valve banks.

Purpose

The safe-state entry point the product's safety thread calls (architecture-port design §3.4 "Hardware enable path", §3.7, §3.8). EnablePins(false) drives MAX22200 ENABLE and TLE92466ED EN low: every solenoid and proportional output is de-energised in hardware, without SPI and without taking the valve manager's mutex. It is the hardware half of SafeHold; the software half (every channel commanded to 0 over SPI) stays with the caller, exactly as today.

This first slice does not decide policy: when to drop the pins, and whether a side is vented before the hold, belong to the product's safety arbiter (owner questions Q1, Q2).

Ownership

Stateless wrapper over ValveManager (DropEnablePins / RearmEnablePins). The rest of the ValveBank facade (set-points, readback) arrives with the composition root.

Thread safety: EnablePins(false) is lock-free and SPI-free (see ValveManager::DropEnablePins). EnablePins(true) re-runs valve bring-up: mutex, SPI, logging; never from the safety path.

Error handling: facade lane, flux::hal::HalResult.

Author

HardFOC Team

Date

2026