SPI transaction configuration. More...

#include <tle92466ed_spi_interface.hpp>

Public Attributes
uint32_t	frequency {1'000'000}
	SPI clock frequency in Hz (max 8 MHz, datasheet 5.1.4 Table 18)

uint8_t	mode {1}
	SPI mode (CPOL=0, CPHA=1 for TLE92466ED)

bool	msb_first {true}
	MSB first transmission.

uint32_t	timeout_ms {100}
	Transaction timeout in milliseconds.

Detailed Description

SPI transaction configuration.

Defines the configuration parameters for SPI communication. CPOL=0, CPHA=1 (SPI Mode 1) for TLE92466ED

From TLE92466ED datasheet: "The falling edge of CSN indicates the beginning of a data access. Data is sampled in on line SI at the falling edge of SCK and shifted out on line SO at the rising edge of SCK. Each access must be terminated by a rising edge of CSN."

Member Data Documentation

◆ frequency

uint32_t tle92466ed::SPIConfig::frequency {1'000'000}

SPI clock frequency in Hz (max 8 MHz, datasheet 5.1.4 Table 18)

◆ mode

uint8_t tle92466ed::SPIConfig::mode {1}

SPI mode (CPOL=0, CPHA=1 for TLE92466ED)

◆ msb_first

bool tle92466ed::SPIConfig::msb_first {true}

MSB first transmission.

◆ timeout_ms

uint32_t tle92466ed::SPIConfig::timeout_ms {100}

Transaction timeout in milliseconds.

The documentation for this struct was generated from the following file: