tle92466ed::CLK_DIV Namespace Reference

CLK_DIV bit definitions. More...

Classes
struct	PllConfig

Functions
constexpr uint16_t	BuildExternalPll (uint8_t pll_refdiv, uint16_t pll_fbdiv) noexcept
	Pack the external-clock PLL configuration.
PllConfig	CalculatePllFromExternalHz (uint32_t f_clk_hz) noexcept

Variables
constexpr uint16_t	EXT_CLK_BIT = (1u << 15)
constexpr uint16_t	PLL_REFDIV_SHIFT = 9u
constexpr uint16_t	PLL_REFDIV_MASK = 0x7E00u
constexpr uint16_t	PLL_FBDIV_MASK = 0x01FFu
constexpr uint32_t	F_SYS_TARGET_HZ = 28'000'000UL
	Target fSYS.
constexpr uint16_t	INTERNAL_OSC = 0x0000u
	Internal-oscillator configuration (no PLL).

Detailed Description

CLK_DIV bit definitions.

Per datasheet \u00a75.3.2.16 p.71. Selects between external clock and the internal oscillator and configures the PLL generating fSYS from the external clock (when EXT_CLK=1): bit 15 EXT_CLK 0 = internal oscillator, 1 = external + PLL bits 14:9 PLL_REFDIV Reference divider R (fREF = fCLK / (R+1)) bits 8:0 PLL_FBDIV Feedback divider N (fSYS = fREF * (N+1))

Resulting system clock must equal 28 MHz \u00b1 tolerances for ICC math to be valid. Typical external clock is 4 or 8 MHz.

Function Documentation

BuildExternalPll()

constexpr uint16_t tle92466ed::CLK_DIV::BuildExternalPll ( uint8_t  pll_refdiv, uint16_t  pll_fbdiv  )

constexprnoexcept

Pack the external-clock PLL configuration.

CalculatePllFromExternalHz()

PllConfig tle92466ed::CLK_DIV::CalculatePllFromExternalHz ( uint32_t  f_clk_hz )

inlinenoexcept

Variable Documentation

EXT_CLK_BIT

constexpr uint16_t tle92466ed::CLK_DIV::EXT_CLK_BIT = (1u << 15)

constexpr

F_SYS_TARGET_HZ

constexpr uint32_t tle92466ed::CLK_DIV::F_SYS_TARGET_HZ = 28'000'000UL

constexpr

Target fSYS.

INTERNAL_OSC

constexpr uint16_t tle92466ed::CLK_DIV::INTERNAL_OSC = 0x0000u

constexpr

Internal-oscillator configuration (no PLL).

PLL_FBDIV_MASK

constexpr uint16_t tle92466ed::CLK_DIV::PLL_FBDIV_MASK = 0x01FFu

constexpr

PLL_REFDIV_MASK

constexpr uint16_t tle92466ed::CLK_DIV::PLL_REFDIV_MASK = 0x7E00u

constexpr

PLL_REFDIV_SHIFT

constexpr uint16_t tle92466ed::CLK_DIV::PLL_REFDIV_SHIFT = 9u

constexpr