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PCA9555 / PCAL9555A Driver
API reference
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Classes | |
| class | I2cInterface |
| CRTP-based template interface for I2C bus operations. More... | |
| class | PCAL95555 |
| Driver for the PCA9555 / PCAL9555A / PCAL95555AHF I²C GPIO expander. More... | |
| struct | PinReadResult |
| Fixed-capacity result container for multi-pin read operations. More... | |
Enumerations | |
| enum class | Pcal95555Reg : uint8_t { INPUT_PORT_0 = 0x00 , INPUT_PORT_1 = 0x01 , OUTPUT_PORT_0 = 0x02 , OUTPUT_PORT_1 = 0x03 , POLARITY_INV_0 = 0x04 , POLARITY_INV_1 = 0x05 , CONFIG_PORT_0 = 0x06 , CONFIG_PORT_1 = 0x07 , DRIVE_STRENGTH_0 = 0x40 , DRIVE_STRENGTH_1 = 0x41 , DRIVE_STRENGTH_2 = 0x42 , DRIVE_STRENGTH_3 = 0x43 , INPUT_LATCH_0 = 0x44 , INPUT_LATCH_1 = 0x45 , PULL_ENABLE_0 = 0x46 , PULL_ENABLE_1 = 0x47 , PULL_SELECT_0 = 0x48 , PULL_SELECT_1 = 0x49 , INT_MASK_0 = 0x4A , INT_MASK_1 = 0x4B , INT_STATUS_0 = 0x4C , INT_STATUS_1 = 0x4D , OUTPUT_CONF = 0x4F } |
| Register addresses for the PCA9555 / PCAL9555A I/O expander chips. More... | |
| enum class | GPIODir : uint8_t { Input = 1 , Output = 0 } |
| enum class | Polarity : uint8_t { Normal = 0 , Inverted = 1 } |
| enum class | DriveStrength : uint8_t { Level0 = 0 , Level1 = 1 , Level2 = 2 , Level3 = 3 } |
| enum class | OutputMode : uint8_t { PushPull = 0 , OpenDrain = 1 } |
| enum class | InterruptEdge : uint8_t { Rising = 1 , Falling = 2 , Both = 3 } |
| enum class | InterruptState : uint8_t { Enabled = 0 , Disabled = 1 } |
| enum class | Error : uint16_t { None = 0 , InvalidPin = 1 << 0 , InvalidMask = 1 << 1 , I2CReadFail = 1 << 2 , I2CWriteFail = 1 << 3 , UnsupportedFeature = 1 << 4 , InvalidAddress = 1 << 5 } |
| enum class | ChipVariant : uint8_t { Unknown = 0 , PCA9555 = 1 , PCAL9555A = 2 } |
| Identifies the detected or user-specified chip variant. More... | |
| enum class | CtrlPin : uint8_t { INTN = 0 , RSTN } |
| Identifies the hardware control pins of the PCAL95555. More... | |
| enum class | GpioSignal : uint8_t { INACTIVE = 0 , ACTIVE = 1 } |
| Abstract signal level for control pins. More... | |
Functions | |
| constexpr Error | operator| (Error lhs, Error rhs) noexcept |
| Combine two Error flags. | |
| constexpr Error | operator& (Error lhs, Error rhs) noexcept |
| Intersect two Error flags. | |
| constexpr Error | operator~ (Error e) noexcept |
| Complement an Error flag (useful with ClearErrorFlags). | |
| const char * | GetDriverVersion () noexcept |
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Identifies the detected or user-specified chip variant.
The driver supports both the standard PCA9555 and the enhanced PCAL9555A. The variant is auto-detected during initialization by probing an Agile I/O register. It can also be forced via the constructor to skip detection.
| Enumerator | |
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| Unknown | Not yet detected (pre-initialization) |
| PCA9555 | Standard PCA9555 (registers 0x00-0x07 only) |
| PCAL9555A | NXP PCAL9555A with Agile I/O (registers 0x00-0x07 + 0x40-0x4F) |
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Identifies the hardware control pins of the PCAL95555.
Used with GpioSet() / GpioRead() to control or read the IC's dedicated GPIO pins through the I2cInterface.
The PCA9555 and PCAL9555A have no reset input (PCAL9555A data sheet Rev. 2, table 3; PCA9555 Rev. 10, table 3): the only reset is power-on reset, and PCAL95555::ResetToDefault() rewrites the power-up register values instead. RSTN is kept only so existing ports still compile.
| Enumerator | |
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| INTN | Interrupt output (active-low, open-drain, read-only) |
| RSTN | No such pin on these parts; never driven by the driver. |
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Error conditions reported by the driver.
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Register addresses for the PCA9555 / PCAL9555A I/O expander chips.
PCAL95555 register map (all control registers).
The register map is split into two banks:
Standard PCA9555 registers (0x00-0x07) - Supported by both PCA9555 and PCAL9555A:
PCAL9555A Agile I/O registers (0x40-0x4F) - PCAL9555A only:
Each register controls 8 pins, with PORT_0 handling pins 0-7 and PORT_1 handling pins 8-15.
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Intersect two Error flags.
Combine two Error flags.