Advanced ESP32-integrated I2C controller for ESP-IDF v5.5+ with proper bus-device architecture.
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#include "BaseI2c.h"
#include "utils/EspTypes.h"
#include "utils/PlatformMutex.h"
#include <memory>
#include <vector>
#include "driver/i2c_master.h"
#include "esp_log.h"
Go to the source code of this file.
Advanced ESP32-integrated I2C controller for ESP-IDF v5.5+ with proper bus-device architecture.
This header provides a comprehensive I2C implementation that properly utilizes the ESP-IDF v5.5+ bus-device model, following the same pattern as the SPI implementation. The architecture separates bus management from device operations, providing clean abstraction and optimal resource management.
ESP32/ESP-IDF v5.5+ Features Supported:
- Bus-Device Architecture: Separate EspI2cBus and EspI2cDevice classes
- Modern API: Uses i2c_new_master_bus() and i2c_master_bus_add_device()
- Mode-Aware Operations: Single mode variable determines sync vs async capabilities
- Per-Device Configuration: Each device has its own clock speed and settings
- Thread Safety: Full RTOS integration with proper synchronization
- Device Management: Dynamic device addition/removal with proper cleanup
- BaseI2c Integration: EspI2cDevice inherits from BaseI2c for portability
- Comprehensive Error Handling: Proper error conversion and reporting
- Resource Management: Automatic cleanup and proper resource lifecycle
Performance Characteristics:
- Standard Mode: 100 kHz
- Fast Mode: 400 kHz
- Fast Mode Plus: 1 MHz (ESP32)
- 7-bit and 10-bit addressing support
- Clock stretching with configurable timeout
- Hardware FIFO utilization
- Multi-master operation capability
- Author
- Nebiyu Tadesse
- Date
- 2025
- Copyright
- HardFOC
- Version
- 4.0.0 - Mode-aware architecture with DRY implementation
- Note
- This implementation requires ESP-IDF v5.5+ and is optimized for ESP32.
-
Thread-safe operation is guaranteed for all public methods.
-
Follows the same architectural pattern as EspSpi for consistency.
-
ESP-IDF v5.5+ enforces strict separation between sync/async modes.
}
uint8_t data[] = {0x10, 0x20, 0x30};
hf_i2c_err_t
Definition BaseI2c.h:85
@ HF_I2C_MODE_SYNC
Sync mode: blocking operations only, no queue.
@ HF_I2C_ADDR_7_BIT
7-bit address
Abstract base class for I2C device implementations.
Definition BaseI2c.h:196
Manages a single I2C bus. Handles bus initialization and device creation.
Definition EspI2c.h:548
RAII soft-CS: runs assert_fn on construction and deassert_fn on destruction (including early return /...
Definition SoftChipSelectGuard.h:32
I2C device configuration structure.
Definition EspTypes_I2C.h:225
I2C master bus configuration structure.
Definition EspTypes_I2C.h:195
}
uint8_t data[] = {0x10, 0x20, 0x30};
});
constexpr std::string_view HfI2CErrToString(hf_i2c_err_t err) noexcept
Convert hf_i2c_err_t to human-readable string.
Definition BaseI2c.h:96
@ HF_I2C_MODE_ASYNC
Async mode: non-blocking operations only, with queue.
◆ hf_i2c_operation_t
Enumeration for I2C operation types used in logging and validation.
| Enumerator |
|---|
| HF_I2C_OP_WRITE | Write operation.
|
| HF_I2C_OP_READ | Read operation.
|
| HF_I2C_OP_WRITE_READ | Write-then-read operation.
|
| HF_I2C_OP_WRITE_ASYNC | Asynchronous write operation.
|
| HF_I2C_OP_READ_ASYNC | Asynchronous read operation.
|
| HF_I2C_OP_WRITE_READ_ASYNC | Asynchronous write-then-read operation.
|
◆ HfI2COperationToString()
Convert operation type to string for logging.
- Parameters
-
- Returns
- String representation of operation