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ADS7952 Driver
API reference
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Template implementation for the ADS7952 driver. More...
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Template implementation for the ADS7952 driver.
Implements all ADS7952 driver methods using direct imperative SPI frame sequences. Each operation sends the required frames inline and returns success/failure — no internal state machine.
SPI Pipeline Model (ADS7952 datasheet SLAS605C, Figure 51): A channel written in frame N is parsed at the CS rising edge that ends frame N, the MUX switches on the 2nd SCLK of frame N+1, the input is acquired during frame N+1 and sampled on the CS falling edge that opens frame N+2. The conversion for that channel is therefore clocked out in frame N+2. Frame N+1 still returns the channel that was selected two frames earlier. Every response carries its own 4-bit channel address in DO15:12; results are keyed on that address, never on frame position: Frame N: MANUAL | channel → stale (discard) Frame N+1: CONTINUE → previous channel (discard) Frame N+2: CONTINUE → DO15:12 == channel → result Auto-1 / Auto-2 follow the same N+2 rule for the first channel of a sequence; ReadAllChannels keys on the address for the same reason.
Acquisition is clocked by SCLK (14th rising edge → next CS falling edge), so the SCLK rate and the CS gap set how long the hold cap has to settle to the new channel. Run the bus at the rate the front end was characterised at (Airseal / Moonshine: 1 MHz) and keep the 16 clocks of one frame contiguous.
Definition in file ads7952.ipp.
1.9.8